Intel E5-2418L 2 GHz Quad Core 10MB SmartCache Processor

Intel Xeon E5-2418L / 00Y8103 / 00Y8135 2 GHz Quad Core 10MB SmartCache Processor - Socket FCLGA1356 - Brand New

Intel Xeon E5-2418L / 00Y8103 / 00Y8135 2 GHz 4 Core 10MB SmartCache Processor - Socket FCLGA1356 - Brand New

Introduction
The Intel® Xeon® Processor E5-2400 Product Family provides DC specifications, signal integrity, differential signaling specifications, land and signal definitions, and an overview of additional processor feature interfaces.

The Intel® Xeon® processor E5-2400 product family is the next generation of 64-bit, multi-core enterprise processors built on 32-nanometer process technology. Throughout this document, the Intel® Xeon® processor E5-2400 product family may be referred to as simply the processor. Based on the low-power/high performance 2nd Generation Intel(r) Core(TM) Processor Family microarchitecture, the processor is designed for a two chip platform consisting of a processor and a Platform Controller Hub (PCH) enabling higher performance, easier validation, and improved x-y footprint. The Intel® Xeon® processor E5-2400 product family is designed for server-class platforms including those for embedded and storage applications with up to two processor sockets. The processor family features one Intel® QuickPath Interconnect (Intel® QPI) point-to-point link capable of up to 8.0 GT/s, up to 24 lanes of PCI Express 3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express 2.0 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space.

Included in this family of processors is an integrated memory controller (IMC) and integrated I/O (IIO) (such as PCI Express and DMI2) on a single silicon die. This single die solution is known as a monolithic processor.

Processor Feature Details

• Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket
• 46-bit physical addressing and 48-bit virtual addressing
• 1 GB large page support for server applications
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data mid-level (L2) cache for each core
• Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores

System Memory Support

• Intel® Xeon® processor E5-2400 product family product family supports three DDR3 channels
• Unbuffered DDR3 and registered DDR3 DIMMs
• LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher capacity memory subsystems
• Independent channel mode or lockstep mode
• Data burst length of eight cycles for all memory organization modes
• Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s
• 64-bit wide channels plus 8-bits of ECC support for each channel
• DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V
• 1-Gb, 2-Gb and 4-Gb DDR3 DRAM technologies supported for these devices:
  • UDIMMs x8, x16
  • RDIMMs x4, x8
  • LRDIMM x4, x8 (2-Gb and 4-Gb only)
• Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM
• Open with adaptive idle page close timer or closed page policy
• Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern
• Minimum memory configuration: independent channel support with 1 DIMM populated
• Integrated dual SMBus master controllers
• Command launch modes of 1n/2n
• RAS Support (including and not limited to):
  • Rank Level Sparing and Device Tagging
  • Demand and Patrol Scrubbing
  • DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device failure. Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode
  • Lockstep mode where channels 2 & 3 are operated in lockstep mode
  • Data scrambling with address to ease detection of write errors to an incorrect address.
  • Error reporting via Machine Check Architecture
  • Read Retry during CRC error handling checks by iMC
  • Channel mirroring within a socket
• Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
• Memory thermal monitoring support for DIMM temperature via two memory signals, MEM_HOT_C{1/23}_N

PCI Express

• The PCI Express port(s) are fully-compliant to the PCI Express Base Specification, Revision 3.0 (PCIe 3.0)
• Support for PCI Express 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s)
• Up to 24 lanes of PCI Express interconnect for general purpose PCI Express devices at PCIe 3.0 speeds that are configurable for up to 6 x4 independent ports
• 4 lanes of PCI Express at PCIe 2.0 speeds when not using DMI2 port (Port 0), also can be downgraded to x2 or x1
• Negotiating down to narrower widths is supported:
  • x16 port (Port 3) may negotiate down to x8, x4, x2, or x1.
  • x8 port (Port 1) may negotiate down to x4, x2, or x1.
  • x4 port (Port 0) may negotiate down to x2, or x1
  • When negotiating down to narrower widths, there are caveats as to how lane reversal is supported.
• Non-Transparent Bridge (NTB) is supported by PCIe Port3a/IOU1. For more details on NTB mode operation refer to PCI Express Base Specification
  • x4 or x8 widths and at PCIe 1.0, 2.0, 3.0 speeds
  • Two usage models; NTB attached to a Root Port or NTB attached to another NTB
  • Supports three 64-bit BARs
  • Supports posted writes and non-posted memory read transactions across the NTB
  • Supports INTx, MSI and MSI-X mechanisms for interrupts on both side of NTB in upstream direction only
• Address Translation Services (ATS) 1.0 support
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.
• PCI Express Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Supports receiving and decoding 64 bits of address from PCI Express.
  • Memory transactions received from PCI Express that go above the top of physical address space (when Intel VT-d is enabled, the check would be against the translated HPA (Host Physical Address) address) are reported as errors by the processor.
  • Outbound access to PCI Express will always have address bits 63 to 46 cleared.
• Re-issues Configuration cycles that have been previously completed with the Configuration Retry status.
• Power Management Event (PME) functions.
• Message Signaled Interrupt (MSI and MSI-X) messages
• Degraded Mode support and Lane Reversal support
• Static lane numbering reversal and polarity inversion support

Direct Media Interface Gen 2 (DMI2)

• Serves as the chip-to-chip interface to the Intel® C600 Series Chipset
• The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2
• Operates at PCI Express 1.0 or 2.0 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of Interrupt” broadcast message when initiated by the processor.
• System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp

Intel® QuickPath Interconnect (Intel® QPI)

• Compliant with Intel QuickPath Interconnect v1.1 standard packet formats
• Implements a full width Intel QuickPath Interconnect port
• Full width port includes 20 data lanes and 1 clock lane
• 64 byte cache-lines
• Home snoop based coherency
• 3-bit Node ID
• 46-bit physical addressing support
• No Intel QuickPath Interconnect bifurcation support
• Differential signaling
• Forwarded clocking
• Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth per port)
  • All ports run at same operational frequency>
  • Reference Clock is 100 MHz>
  • Slow boot speed initialization at 50 MT/s
• Common reference clocking (same clock generator for both sender and receiver)
• Intel® Interconnect Built-In-Self-Test (Intel® IBIST) for high-speed testability
• Polarity and Lane reversal (Rx side only)

Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH).

• Supports operation at up to 2 Mbps data transfers
• Link layer improvements to support additional services and higher efficiency over PECI 2.0 generation
• Services include CPU thermal and estimated power information, control functions for power limiting, P-state and T-state control, and access for Machine Check Architecture registers and PCI configuration space (both within the processor package and downstream devices)
• PECI address determined by SOCKET_ID configuration
• Single domain (Domain 0) is supported

Compatibility:

Alternate MPNs: 00Y8103 00Y8135

Weight: 1 lb

Warranty: 1 Year DiscTech

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